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[资料] Cyclone IV 器件中的时钟网络与 PLL

发表于 2015-12-10 11:29:49 | 显示全部楼层 |阅读模式 来自 广东省深圳市罗湖区
本章节包含以下几部分内容:
■  时钟网络(第5-1页)
■  Cyclone IV器件中的PLL(第5-18页)
■  Cyclone IV PLL硬件概述(第5-20页)
■  时钟反馈模式(第5-23页)
■  硬件特性(第5-26页)
■  可编程带宽(第5-32页)
■  相移的实现(第5-32页)
■  PLL级联(第5-33页)
■  PLL重配置(第5-34页)
■  扩频时钟(第5-41页)
■  PLL规范(第5-41页)
时钟网络
Cyclone IV GX器件提供了多达12个专用时钟管脚(CLK[15..4]),以用于驱动全局时
钟(GCLKs)。Cyclone IV GX器件的每一侧(左侧除外)支持四个专用时钟管脚,这些
时钟管脚能够驱动高达30个GCLK。
Cyclone IV E器件提供了多达15个专用时钟管脚 (CLK[15..1]),以用于驱动高达20
个GCLK。Cyclone IV E器件的左侧支持三个专用时钟管脚,在顶端、底部及右侧支持
四个专用时钟管脚(EP4CE6与EP4CE10器件除外)。EP4CE6和EP4CE10器件仅在器件
左侧支持三个专用时钟管脚,在器件右侧支持四个专用时钟引脚。
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发表于 2020-1-10 09:57:41 | 显示全部楼层 来自 陕西省西安市
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