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eMCP Specification
32GB eMMC (x8) + 32Gb LPDDR4X (x32, 2CH/2CS)
FEATURES
[ eMCP ]
● Operation Temperature
- (-25) o C ~ 85 o C
● Package
- 254-ball FBGA
- 11.5x13.0mm 2 , 1.2t, 0.5mm pitch
- Lead & Halogen Free
[ eMMC ]
• eMMC5.1 compatible
(Backward compatible to eMMC4.5&eMMC5.0)
• Bus mode
- Data bus width : 1bit(default), 4bits, 8bits
- Data transfer rate: up to 400MB/s (HS400)
- MMC I/F Clock frequency : 0~200MHz
- MMC I/F Boot frequency : 0~52MHz
• Operating voltage range
- V cc (NAND) : 2.7V - 3.6V
- V ccq (Controller) : 1.7V - 1.95V / 2.7V ~ 3.3V
• Temperature
- Operation (-25 ℃ ~ +85 ℃ )
- Storage without operation (-40 ℃ ~ +85 ℃ )
• Others
- This product is compliance with the RoHS
directive
• Supported features
- HS400, HS200
- HPI, BKOPS, BKOP operation control
- Packed CMD, CMD queuing
- Cache, Cache barrier, Cache flushing
report
- Partitioning, RPMB, RPMB throughput improve
- Discard, Trim, Erase, Sanitize
- Write protect, Secure write protection
- Lock/Unlock
- PON, Sleep/Awake
- Reliable Write
- Boot feature, Boot partition
- HW/SW Reset
- Field firmware Update
- Configurable driver strength
- Health(Smart) report
- Production state awareness
- Secure reMOVal type
- Data Strobe pin, Enhanced data strobe
(Bold features are added in eMMC5.1)
[ LPDDR4X ]
· VDD1 = 1.8V (1.7V to 1.95V)
· VDD2 = 1.1V (1.06V to 1.17V)
· VDDQ = 0.6V (0.57V to 0.65V)
· Programmable CA ODT and DQ ODT with VSSQ termi-
nation
· VOH compensated output driver
· Single data rate command and address entry
· Double data rate architecture for data Bus;
- two data accesses per clock cycle
· Differential clock inputs (CK_t, CK_c)
· Bi-directional differential data strobe (DQS_t, DQS_c)
· DMI pin support for write data masking and DBIdc
functionality
· Programmable RL (Read Latency) and WL (Write La-
tency)
· Burst length: 16 (default), 32 and On-the-fly
- On the fly mode is enabled by MRS
· Auto refresh and self refresh supported
· All bank auto refresh and directed per bank auto re-
fresh supported
· Auto TCSR (Temperature Compensated Self Refresh)
· PASR (Partial Array Self Refresh) by Bank Mask and
Segment Mask
· Background ZQ Calibration
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