海力士H9HQ15AFAMADAR NAND闪存datasheet规格说明

jianghuiyan

海力士H9HQ15AFAMADAR UFS产品由NAND闪存和UFS控制器组成。 UFS内置智能控制器，管理接口协议、磨损平整、坏块管理、垃圾收集还有ECC。 第一个SKhynix的UFS与JEDEC标准UFS2.1规范兼容，支持UniProv1.61和M-PHYv3.0(HS-G1/G2/G3速率A/B，PWM-G1/G2/G3/G4，双车道)

FEATURES
[ uMCP ]
● Operation Temperature
- (-25)oC ~ 85oC
● Package
- 254-ball FBGA
- 11.5x13.0mm2, 1.1t, 0.5mm pitch
- Lead & Halogen Free
[ UFS ]
• UFS2.1 compatible
- backward compatibility with UFS2.0
• Operating Voltage Range
- V
cc (NAND) : 2.7V - 3.6V
- V
ccq (CTRL) : Not Used
- V
ccq2 (CTRL) : 1.7V - 1.95V
• Temperature
- Operation Temperature (-25℃ ~ +85℃ )
- Storage Temperature (-40℃ ~ +85℃ )
• Reference
- JEDEC UFS SPECification V2.1
- mipi UniPro Specification V1.61
- MIPI M-PHY Specification V3.0
• supported Features
- Erase / Discard / Purge / Wipe
- PWM G1~G4 / HS-G1~G3
- 1L/2L
- Command Queuing / Cache
- RPMB / BOOT LU
- power-on/HW/EndPoint/LU Reset
- BKOP
- High Priority LU
- Reliable Write Operation
- Write Protect, Secure Write Protect
- Task Management operations
- Secure ReMOVal Type
- Power Management operations
- MAX 32 LU supported
- device Health Descriptor
- Field firmware Update
[ LPDDR4X ]
· VDD1 = 1.8V (1.7V to 1.95V)
· VDD2 = 1.1V (1.06V to 1.17V)
· VDDQ = 0.6V (0.57V to 0.65V)
· Programmable CA ODT and DQ ODT with VSSQ termination
· VOH compensated output driver
· Single data rate command and address entry
· Double data rate architecture for data Bus;
- two data accesses per clock cycle
· Differential clock inputs (CK_t, CK_c)
· Bi-directional differential data strobe (DQS_t, DQS_c)
· DMI pin support for write data masking and DBIdc
functionality
· Programmable RL (Read Latency) and WL (Write Latency)
· Burst length: 16 (default), 32 and On-the-fly
- On the fly mode is enabled by MRS
· Auto refresh and self refresh supported
· All bank auto refresh and directed per bank auto refresh supported
· Auto TCSR (Temperature Compensated Self Refresh)
· PASR (Partial Array Self Refresh) by Bank Mask and
Segment Mask
· Background ZQ Calibration