totally hardware-based maximum 48-Megapixel ISP (image signal processor). It implements a lot of algorithm accelerators, such as HDR, 3A, LSC, 3DNR, 2DNR, sharpening, dehaze, fisheye correction, gamma correction and so on.
The build-in NPU supports INT4/INT8/INT16/FP16 hybrid operation and computing power is up to 6TOPs. In addition, with its strong compatibility, network models based on a series of Frameworks such as TensorFlow/MXNet/PyTorch/Caffe can be easily converted. RK3588 has high-performance quad channel external memory interface (LPDDR4/LPDDR4X/LPDDR5) capable of sustaining demanding memory bandwidths, also provides a complete set of peripheral interface to support very flexible applications.
1.2 Features
The features listed below which may or may not be present in actual product, may be subject to the third party licensing requirements. Please contact Rockchip for actual product feature configurations and licensing requirements.
1.2.1 Microprocessor
Quad-core ARM Cortex-A76 MPCore processor and quad-core ARM Cortex-A55 MPCore processor, both are high-performance, low-power and cached application processor
DSU (DynamIQ Shared Unit) comprises the L3 memory system, control logic, and external interfaces to support a DynamIQ cluster
Full implementation of the ARM architecture v8-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerating media and signal processing
ARMv8 Cryptography Extensions
Trustzone technology support
Integrated 64KB L1 instruction cache, 64KB L1 data cache and 512KB L2 cache for each Cortex-A76
Integrated 32KB L1 instruction cache, 32KB L1 data cache and 128KB L2 cache for each Cortex-A55
Quad-core Cortex-A76 and Quad-core Cortex-A55 share 3MB L3 cache
Eight separate power domains for CPU core system to support internal power switch and externally turn on/off based on different application scenario
PD_CPU_0: 1st Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
PD_CPU_1: 2nd Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
PD_CPU_2: 3rd Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
PD_CPU_3: 4th Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
已绑定手机
发表于 2022-5-30 18:18
