DATA INPUTS/OUTPUTS
The DQ pins allow to input command, address and data and to output data during read / program operations. The inputs are latched on the rising edge of Write Enable (WE#). The I/O buffer float to High-Z when the device is deselected or the outputs
are disabled.
CLE
COMMAND LATCH ENABLE
This input activates the latching of the DQ inputs inside the Command Register on the Rising edge of Write Enable (WE#).
ALE
ADDRESS LATCH ENABLE
This input activates the latching of the DQ inputs inside the Command Register on the Rising edge of Write Enable (WE#).
CE#
CHIP ENABLE
This input controls the selection of the device. When the device is busy CE# low does not deselect the memory.
WE#
WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The DQ inputs are latched on the rise edge of WE#.
RE#
READ ENABLE
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE# which also increments the internal column address counter by one.
WP#
WRITE PROTECT
The WP# pin, when Low, provides an Hardware protection against undesired modify (program / erase) operations.
RB#
READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC
SUPPLY VOLTAGE
The VCC supplies the power for all the operations (Read, Write, Erase). An internal lock circuit prevent the insertion of Commands when VCC is less than VLKO