| Pin No. | Pin Name | Pin Type | Description |
| 1 | REFIN | I | Reference voltage input for output voltage regulation. |
| 2 | VREF | O | 2.0 V output reference voltage. A 10 nF ceramic capacitor is required to connect this pin to ground. |
| 3 | VRMP | I | Feed−forward input of VIN for the ramp slope compensation. |
| 4 | SS | I/O | Soft Start setting. During startup it is used to program the soft start time with a resistor to ground. |
| 5 | I2C | I/O | I2C address. During startup it is used to program I2C address with a resistor to ground. |
| 6 | LPC1 | I/O | Low phase count 1. During startup it is used to program warm boot−up power zone (PSI set low) |
| 7 | LPC2 | I/O | Low phase count 2. During startup it is used to program cold boot−up power zone (PSI set low) |
| 8 | PWM4/PHTH1 | I/O | PWM 4 output / Phase Shedding Threshold 1. During startup it is used to program the phase shedding threshold 1(PSI set to mid state) with a resistor to ground. |
| 9 | PWM3/PHTH2 | I/O | PWM 3 output / Phase Shedding Threshold 2. During startup it is used to program the phase shedding threshold 2 (PSI set to mid state) with a resistor to ground. |
| 10 | PWM2/PHTH3 | I/O | PWM 2 output / Phase Shedding Threshold 3. During startup it is used to program the phase shedding threshold 3 (PSI set to mid state) with a resistor to ground. |
| 11 | PWM1/PHTH4 | I/O | PWM 1 output / Phase Shedding Threshold 4. During startup it is used to program the phase shedding threshold 4 (PSI set to mid state) with a resistor to ground. |
| 12 | DRON | I/O | Bidirectional gate driver enable for external drivers. |
| 13 | NC | N/A | Not connected, leave it floating. |
| 14 | NC | N/A | Not connected, leave it floating. |
| 15 | NC | N/A | Not connected, leave it floating. |
| 16 | NC | N/A | Not connected, leave it floating. |
| 17 | CSP4 | I | Non−inverting input to current balance sense amplifier for phase 4. Pull−up to VCC with a 2 kQ resistor to disable the PWM4 output. |
| 18 | CSP3 | I | Non−inverting input to current balance sense amplifier for phase 3. Pull−up to VCC with a 2 kQ resistor to disable the PWM3 output. |
| 19 | CSP2 | I | Non−inverting input to current balance sense amplifier for phase 2. Pull−up to VCC with a 2 kQ resistor to disable the PWM2 output. |
| 20 | CSP1 | I | Non−inverting input to current balance sense amplifier for phase 1. Pull−up to VCC with a 2 kQ resistor to disable the PWM1 output. |
| 21 | CSREF | I | Total output current sense amplifier reference voltage input. |
| 22 | CSSUM | I | Inverting input of total current sense amplifier. |
| 23 | CSCOMP | O | Output of total current sense amplifier |
| 24 | ILIM | I/O | Over current limit (OCL) threshold setting input. The threshold is set by a shunt resistor to the ground. |
| 25 | IOUT | O | Total output current. A resistor to GND is required to provide a voltage drop of 2 V at the maximum output current. |
| 26 | TMON | I | DRMOS temperature monitoring |
| 27 | FSW | I | Resistor to ground from this pin sets the operating frequency of the regulator. |
| 28 | DIFF | O | Output of the regulators differential remote sense amplifier. |
| 29 | FB | I | Error amplifier inverting (feedback) input. |
| 30 | COMP | O | Output of the error amplifier and the inverting input of the PWM comparator. |
| 31 | VSP | I | Differential Output Voltage Sense Positive terminal. |
| 32 | VSN | I | Differential Output Voltage Sense Negative terminal. |
| 33 | VCC | I | Power for the internal control circuits. A 1 µF decoupling capacitor is requires from this pin to ground. |
| 34 | SDA | I/O | Serial Data bi−directional pin, requires pull−up resistor to VCC. |
| 35 | SCL | I | Serial Bus clock pin, requires pull−up resistor to VCC. |
| 36 | EN | I | Logic input. Logic high enables regulator output logic low disables regulator output. |
| 37 | PSI | I | Power Saving Interface control pin. This pin can be set low, high or left floating. |
| 38 | PGOOD | O | Open Drain power good indicator. |
| 39 | PWM_VID | I | PWM_VID buffer input. |
| 40 | VID_BUFF | O | PWM_VID pulse output from internal buffer. |
| 41 | AGND | GND | Analog ground and thermal pad, connected to system ground. |
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发表于 2022-8-16 17:52
