Core and System |
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8051 | Fully static design 8-bit high performance 1T 8051-based CMOS microcontroller.
Instruction set fully compatible with MCS-51.
4-priority-level interrupts capability.
Dual Data Pointers (DPTRs). |
Power on Reset (POR) | POR with 1.55V threshold voltage level |
Brown-out Detector (BOD) | 7-level selection, with brown-out interrupt and reset option. (4.4V / 3.7V / 3.0V / 2.7V / 2.4V / 2.0V / 1.8V) |
Low Voltage Reset (LVR) | LVR with 1.63V threshold voltage level |
Security | 96-bit Unique ID (UID)
128-bit Unique Customer ID (UCID)
128-bytes security protection memory SPROM |
Memories |
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Flash | Up to 64 KBytes of APROM for User Code.
4/3/2/1 Kbytes of Flash for loader (LDROM) configure from APROM for In-System-Programmable (ISP)
Flash Memory accumulated with pages of 128 Bytes from APROM by In-Application-Programmable (IAP) means whole APROM can be use as Data Flash
An additional 128 bytes security protection memory SPROM
Code lock for security by CONFIG |
SRAM | 256 Bytes on-chip RAM.
Additional 4 KBytes on-chip auxiliary RAM (XRAM) accessed by MOVX instruction. |
file:///C:\Users\ADMINI~1\AppData\Local\Temp\ksohtml\clip_image2.pngPDMA: | Three modes: peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer.
Source address and destination address must be word alignment in all modes.
Memory-to-memory mode: transfer length must be word alignment. |
Clocks |
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External Clock Source | 4~24 MHz High-speed external crystal oscillator (HXT) for precise timing operation
32.768 kHz High-speed external crystal oscillator (LXT) for RTC operation |
Internal Clock Source | Default 24 MHz high-speed internal oscillator (HIRC) trimmed to ±1% (accuracy at 25 °C, 3.3 V), ±2% in -20~105°C.
38.4 kHz low-speed internal oscillator (LIRC) calibrating to
±2% by software from high-speed internal oscillator |
Timers |
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16-bit Timer | Two 16-bit Timers/Counters 0 and 1 compatible with standard 8051.
One 16-bit Timer 2 with three-channel input capture module and 9 input pin can be selected.
One 16-bit auto-reload Timer 3, which can be the baud rate clock source of UARTs. |
Watchdog | 6-bit free running up counter for WDT time-out interval.
Selectable time-out interval is 1.66 ms ~ 3413.12 ms since WDT_CLK = 38.4 kHz (LIRC).
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out |
Wake-up Timer | 8-bit free running up counter for time-out interva for ML51 32KB / 16KB flash series.
16-bit free running up counter for time-out interva for ML56 / ML54 / ML51 64KB flash series.
Clock sources from LIRC or LXT.
Able self Wake-up wake up from Power-down or Idle mode, and auto reload count value.
Supports Interrupt |
PWM | Up To 12 output pins can be selected
Supports maximum clock source frequency up to 24 R/W
Supports up to Four PWM modules, One module provides 6 output channels other 3 each provides 2 channels.
Supports independent mode for PWM output
Supports complementary mode for 3 complementary paired PWM output channels
Dead-time insertion with 9-bit resolution
Supports 16-bit resolution PWM counter
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Supports trigger ADC on the following events |
RTC | Supports real time counter and calendar counter for RTC time and calendar check.
Supports alarm time and calendar settings
Supports alarm time and calendar mask enable settings.
Selectable 12-hour or 24-hour time scale setting.
Supports Leap Year indication setting.
Supports Day of the Week counter setting.
Frequency of RTC clock source compensate by RTC_FREQADJ register.
All time and calendar message expressed in BCD format.
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second.
Supports RTC Time Tick and Alarm Match interrupt.
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is generated.
Support clock source selectable from LXT or LIRC. |
Analog Interfaces |
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Analog-to-Digital Converter (ADC) | Analog input voltage range: 0 ~ AVDD.
External or internal Voltage reference input selectable.
12-bit resolution and 10-bit accuracy is guaranteed.
Up to 16 single-end analog input channels
1 internal channels, they are band-gap voltage (VBG).
Maximum ADC peripheral clock frequency is 1 MHz.
Up to 500 KSPS sampling rate.
Software Write 1 to ADCS bit to trig ADC start.
External pin (STADC) trigger
PWM trigger. |
Communication Interfaces |
UART | Supports up to 2 UARTs: UART0, UART1
Supports 2 Smart Card configuration as UART function as UART2 and UART3.
UART baud rate clock from HIRC or HXT.
Full-duplex asynchronous communications
Programmable 9th bit.
TXD and RXD pins of UART0 exchangeable via software. |
I2C | 2 sets of I2C devices
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
7-bit addressing mode
Standard mode (100 kbps) and Fast mode (400 kbps).
Supports 8-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-out counter overflows
Multiple address recognition (four slave addresses with mask option)
Supports hold time programmable |
SPI | 2 sets of SPI devices
Supports Master or Slave mode operation
Supports MSB first or LSB first transfer sequence
Slave mode up to 12 Mhz |
ISO 7816-3 | Two sets ISO 7816-3 device
Supports ISO 7816-3 compliant T=0, T=1
Supports full-duplex UART mode. |
GPIO | Four I/O modes:
Quasi-bidirectional mode
Push-Pull Output mode
Open-Drain Output mode
Input only with high impendence mode
Schmitt trigger input / TTL mode selectable.
Each I/O pin configured as interrupt source with edge/level trigger setting
Standard interrupt pins INT0 and INT1.
Supports high drive and high sink current I/O
I/O pin internal pull-up or pull-down resistor enabled in input mode.
Maximum I/O Speed is 24 MHz
Enabling the pin interrupt function will also enable the wake- up function
Supports 5V-tolerance function for ML51 64KB Flash/ML54/ML56 Series |