Pin Name | Description | Pin Name | Description |
A0-A16 | SDRAM address bus | SCL | I2C serial bus clock for SPD-TSE |
BA0, BA1 | SDRAM bank select | SDA | I2C serial bus line for SPD-TSE |
BG0, BG1 | SDRAM bank group select | SAO-SA2 | I2C slave address select for SPD-TSE |
RAS n¹ | SDRAM row address strobe | PARITY | SDRAM parity input |
CAS n² | SDRAM column address strobe | VDD | SDRAM I/OO and core power supply |
file:///C:\Users\ADMINI~1\AppData\Local\Temp\ksohtml\clip_image2.pngWE n³ | SDRAM write enable | VPP | SDRAM activating power supply |
CS0 n, CS1 n,
CS2 n,CS3 n | Rank Select Lines | C₀ ,C1 | Chip ID lines for 3DS components |
CKEO, CEK1 | SDRAM clock enable lines input | VREFCA | SDRAM command/address reference
supply |
ODTO, ODT1 | SDRAM on-die termination control
lines input | VSS | Power supply return (ground) |
ACT n | SDRAM activate | VDDSPD | Serial SPD-TSE positive power supply |
DQ0-DQ63 | DIMM memory data bus | ALERT n | SDRAM ALERT n output |
CBO-CB7 | DIMM ECC check bits | | |
file:///C:\Users\ADMINI~1\AppData\Local\Temp\ksohtml\clip_image3.pngDQSO t-DQS8 t | SDRAM data strobes
(positive line of differential pair) | RESET n | Set DRAMs to a Known State |
DQSO c-DQS8 c | SDRAM data strobes
(negative line of differential pair) | EVENT n | SPD signals a thermal event has
occurred |
DMO n-DM8 n,
_ _
DBIO n-DBI8 n
_ _ | SDRAM data masks/data bus inersion
(x8-based x72 DImms) | VTT | SDRAM I/O termination supply |
CKO t, CK1 t | SDRAM clock (positive line of differen-
tial pair) | NC | No connection |
CKO c,CK1 c | SDRAM clock (positive line of differen ·
tial pair) | | |
1. RAS_n是一个与A16复用的函数。