| Feature | SM8650/SM8650P capability |
|
| Applications | Kryo CPU subsystem
■ Prime and high-performance cores for intensive tasks (1 + 5 + 2)
■ Power-efficient cores |
| Digital signal processing and artificial intelligence | ■ Hexagon Tensor Processor
□ V75 AI-optimized tensor processor
□ Six scalar threads with enhanced micro architecture
□ 4x HVX vector tightly couple coprocessors optimized for pixel processing
□ 1x HMX matrix tightly couple coprocessor optimized for deep neural network processing, MAC arithmetic formats include INT8, A16W8, A8W4, and FP16
□ Large VTCM
□ BW compression
□ Improved power efficiency
■ AI use cases
□ Noise reduction
□ Super resolution
□ ML ISP
□ HDR
□ Image enhancement
□ Segmentation
□ Depth estimation
□ Classification/detection
■ For imaging, video, audio, and data-based NN use cases.
■ The hexagon CP is a vision and imaging hardware accelerator to offload and accelerate the hexagon software algorithmic functions.
■ The audio/sensors hexagon DSP is dedicated to the low-power AI subsystem with support for always-on, low-power use cases. It incorporates a dedicated AI processor for offloading neural network use cases to improve the performance and minimize power consumption.
■ All hexagon DSP is cache-based processors with full access to DDR memory for large memory requirements. |
| Always-on system | Always-on subsystem with always-on processor
Hardware-based resource and power management (RPMh) with hardware accelerators for voltage control and regulation, clock management, and resource communication |
|
| Modem | 3G/4G/5G – mmWave and sub-6 bands (Rel 17) only for SM8650 |
| Location | Gen9 v6 LocTech 23 SW
GPS L1/L5/L2C, GLO G1, BDS B1I/B1C/B2A/B2B, GAL E1/E5A/E5B, QZSS L1/L5/L2C, NavIC L5
An analog GNSS interface to the transceiver IC |
|
| System memory via EBI on PoP | Four-channel PoP high-speed memory – LPDDR5X SDRAM (4 × 16‑bit) supports up to 4.2 GHz with system cache |
Storage Via UFS
Via SDC | UFS 4.0 gear 5 Rate B, 1x 2-lane
ICE with 4500 MB/s read and 4000 MB/s write SD v3.0 4 bit for SD card |
|
| Qualcomm® Adreno™ display processing unit (DPU) | DPU1395
■ Maximum resolution for internal panel: Support up to 3360 × 1600 at 144 Hz, 2520 × 1200 at 240 Hz
■ Supports dual MIPI-DSI ports, with support for split-link for fold use case.
■ External panel support: DisplayPort v1.4 with MST (2x 4K60 10‑bit or 1x 8K30 with DSC)
■ Compression support: 6x DSC v1.2
■ Processing: HDR10/10+, HDR Vivid, Dolby Vision HDR, wide color gamut, scaling (improved quality on edge/corner/angle), SPR, and demura (improved quality)
■ Power-saving: Local tone mapping, QSync, variable refresh rate, panel self-refresh using LLC |
| Camera support | ■ Qualcomm spectra image signal processor
□ Qualcomm spectra ISP supports connectivity to multiple cameras due to six included C- PHY/D-PHY interfaces. Furthermore, up to 5 cameras may operate concurrently due to the Qualcomm spectra's 3 IFEs, 2 IFE-lites, and 3 SFEs
■ AI assisted camera with object-based pixel processing in single-camera and multicamera mode
■ Flicker correction improvements in HDR
■ 2 × always sensing camera support for simultaneous front and rear AOC with increased input resolution up to 1080p
□ CSI4 and CSI2 with PM8010 SPMI interface, CAM_MCLK_4 (GPIO_104), and CAM_MCLK_2 (GPIO_102)
□ QR code detection, rotation, and improved face detection accuracy
■ Hardware interface
□ Triple 36 MP ISPs
□ Six combo-PHYs with 4 lanes for D-PHY and 3 trios for C-PHY each
– D-PHY v1.2: 2.5 Gbps/lane
– C-PHY v2.0: 13.68 Gbps/trio
□ Connect up to 12x/18x cameras, 5x concurrent
■ Throughput
□ 108 MP at 30 fps ZSL with in-ISP pixel binning
□ 64 MP at 30 fps ZSL with 2 IFEs combined, without in-ISP binning
□ 200 MP non-ZSL snapshot capture
□ 12 MP at 240 fps fast shutter sensor support - PHY and RAW dump
■ Key improvements
□ Three concurrent 2 × 2/4 × 4/sHDR with motion improvement
□ Seamless switch to fast readout and 108 MP capture
□ Dynamic low voltage operation
■ ZSL example:
□ (36 M + 36 M + 36 M) at 30 fps - triple camera
□ (64 M + 36 M) at 30 fps - dual camera
□ 108 M at 30 fps - single camera
■ MFHDR for snapshot, video, preview
■ Staggered HDR (overlap and nonoverlap) for snapshot, video, and preview |
| EVA | ■ Hardware-based DL-FD 2.6 and DL-FL 2.0
■ A depth processor for iTOF
■ Reprojection and grid inversion engine (RGE)
■ Dense motion map (SGM based OF, 1080p at 60 fps)
■ Depth from stereo (SGM-based DFS, 720p at 60 fps), concurrent with DMM |
| Adreno video processing unit (VPU) | Adreno VPU 8650
UHD 8K video processing unit
Video decode up to 4K at 240 fps/8K at 60 fps and video encode up to 4K at 120 fps/8K at 30 fps Concurrent decode up to 4K at 60 fps and encode up to 4K at 60 fps for wireless display
Max 24 concurrent stream support
Native decode support for H.264, H.265, VP9, and AV1 formats Native encode support for H.264 and H.265 formats
Slice-based encoder support for low-latency performance Max 8192 × 4320/Min 96 × 96 resolution of frame support
Loss frame compression (UBWC) support |
| Adreno graphic processing unit (GPU) | Adreno GPU A750
OpenGL ES 3.2, Vulkan 1.3 OpenCL 3.0 full profile Adreno NN direct Ray tracing pipelines
GMEM improvements for compute and graphics |
| Low power AI subsystem | Merged low-power island, for always-on audio/voice, sensors, sensing hub, and always sensing camera
■ Hexagon V73M 2 × cluster – 4 Thread DSP
■ 8.5 MB of LPI memory
□ 3 MB TCM (DSP and LPAI)
□ 5.5 MB of LPI LLC
■ Dual eNPU4 AI processor to accelerate neural networking use cases
■ Qualcomm Sensing Hub 4.0 |
| Sensors hardware | ■ Data acquisition engine (DAE) - buffer to enable batching of sensor data without waking up the DSP
■ Context change detector (CCD) 5.1
□ Hardware blocks to detect potential changes in context that are validated in software
□ Wakes up DSP once context changes are detected |
| Sensors interfaces and supported sensors | ■ Eleven dedicated buses
□ 2 I3C/I2C, 2 SPI, 2 I2C, 2 UART
□ 2 I3C/I2C, 1 I2C for ASC
■ 7 × I3C IBI for DAE and DSP
■ Sensors supported in QTI POR:
□ 2 × Accelerometer/Gyroscope
□ Magnetometer
□ Ambient Light/Proximity
□ Pressure
□ Humidity/Temperature
□ SAR
□ Hall
□ Always sensing camera
□ Plus others per customer inputs with I3C, I2C, UART, SPI interface could be supported |
| Qualcomm Sensing Hub (QSH) supported technologies | ■ QSH enables multiple data streams providing enhanced contextual data from:
□ Sensors
□ Always sensing camera
□ Audio
□ WWAN
□ Location/Geofencing
□ BLE
□ Wi-Fi |
| Audio and voice hardware | ■ Hardware linear echo cancellation accelerator
■ DSP-offload for audio playback (analog, Bluetooth audio, USB digital audio) |
| Audio interfaces | SLIMbus for WCN785x SoundWire
■ SoundWire interface (3 Tx and 2 Rx data lanes for codec) WCD9395, PMIC haptics
■ Two dedicated SoundWire interfaces to support up to 4 WSA884x for smart speaker amplifier DMICs
■ 4 DMIC ports support up to 8 DMICs
■ Up to 4 DMICs for low-power voice activation I2S
■ 6 I2S with 2x data lanes to support full duplex stereo, or up to 4 channel Tx/Rx application
■ 1 I2S supports 4 data lanes for up to 8 channels Tx/Rx application
TDM/PCM: Up to 32 channels at 48 kHz per individual interface (Qualcomm Technologies, Inc. (QTI) I2S supports both TDM and PCM modes.) |
| Audio and voice algorithms | Voice UI
■ Snapdragon Voice Activation keyword detection
■ Echo cancellation and noise suppression (ECNS) Voice call
■ AI-based noise suppression
■ Far-end noise suppression Audio record
■ Ambient noise suppression
■ HDR record |
| Codec | Integrated within the WCD9395 high fidelity audio codec |
| Speaker amplifier | Integrated within the WSA8840/WSA8845/WSA8845H class-H, low noise smart amplifier |
|
| I/Os | Dual voltage (1.2 V/1.8 V) support. For details, see Pin definitions. |
| Qualcomm universal peripheral (QUP) ports | Qualcomm universal peripheral (QUP) v3 support. 16 QUP serial engines + 11 SSC-QUP serial engines
■ UART
■ I2C
■ I3C
■ SPI
10 I2C hubs |
| USB | ■ One USB 3.1 ports: Gen 2 10 Gbps (DisplayPort + data), support Type-C with DisplayPort v1.4, embedded USB (eUSB2) |
| UIM | Two 1.8 V/3 V SIM card using external level shifter |
| PCIe | 2-lane Gen 3
2-lane Gen 4 |
| Secure digital interfaces | ■ Two 4‑bit ports (SDC2 and SDC4)
■ SDC2: 1.2 V only; SD 3.0
■ 1.8 V/3 V SD card operation using external level shifter
■ SDC4: dual-voltage, SDIO 3.0 |
| Touchscreen support | ■ Capacitive panels via ext IC (I2C, I3C, SPI, and interrupts) |
| Fingerprint support | Ultrasonic Qualcomm® Fingerprint Sensors for under glass, under metal, or under OLED display
QFS4008, QFS2608, QFS2630 |
|
| Number of GPIOs | 210 – GPIO_0 to GPIO_209 |
|
| Crypto | AES-GCM, HW ECC, RSA, SHA2 and SHA3, ICE crypto engine v5 (CE5), FIPS/CAVP 140-3
certified, PRNG compliant to NIST 800-90B |
| QFPROM | Fuse bits available for OEM use |
| Access control | Programmable security domain protection and sandboxing |
| Secure boot and tools | Secure boot/debug security with Sectools 2.0; easy to use tool set |
| Key management | Hardware key manager |
| User data encryption | File-based encryption (FBE) |
| Memory protection | DRAM memory protection for EEs (TEEs and VMs) |
| Storage security | Secure file system (SFS); fast trusted storage |
| TrustZone | Qualcomm® Trusted Execution Environment (QTEE v5.x) |
| Hypervisor | Qualcomm® Type-1 hypervisor enables multiple trusted VMs (TVMs), Google AVF support |
| DSP security | DSP secure domain |
| HLOS kernel security | Qualcomm® runtime kernel security (QRKS) |
| Cellular connection security | Qualcomm® cellular connection security |
| QTEE and TVM services | DRM Widevine V18 L1, HDCP v2.3, Qualcomm® content protection, IP protection Framework, camera security framework, trusted UI framework, trusted location, trusted time, QC WES device attestation service, QC WES secure provisioning service, QC WES third-party feature licensing service |
| SPU | SPU for SoC independent TCB, Android Strong box security |
|
| Boot | See SM8650 Boot and CoreBSP Architecture Overview (80-TBD-11) for the details of boot sequence.
Emergency boot over USB 3.1 |
| PLLs and clocks | ■ 76.8 MHz X'tal
■ Multiple clock regimes; watchdog and sleep timers
■ Input: 38.4 MHz CXO
■ General-purpose outputs: M/N counter and PDM |
| Debug | JTAG, design for software debug (DFSD), embedded USB debug (EUD) |
| Others | Thermal sensors; modes and resets; peripheral subsystem |
Chipset interface features |
| Power management | SPMI; also I2C as needed |
Wireless connectivity WLAN
Bluetooth | PCIe interface SLIMbus/UART interface |
Fabrication technology, package, and major companion ICs |
| Digital die | 4 nm process |
| Package | 1629 MPSP |
| PoP– small, thermally efficient package | 16.5 × 14.0 × 0.56 mm |
WLAN/Bluetooth RF
PMIC
Audio | WCN7850, WCN7851
SDR875 (4G/Sub-6/mmW/GNSS), SDR753 (4G/Sub-6/GNSS) QTM565 (mmW) PM8550, PMK8650, PM8550B/BH/BHS, PM8550VE/VS, PM8010 × 2, PMR735D WCD9395, WSA8840/WSA8845/WSA8845H |
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发表于 2023-10-18 11:01
