Signal Name | BGA Pin | Pad type(1) | Description | Comments |
MRXCP | G2 | DS | MIPI RX clock lane positive input | Sensor Power
Domain |
MRXCN | F2 | I DS | MIPI RX clock lane negative input |
MRXDP0 | G1 | l DS | MIPI RX data lane 0 positive input |
MRXDNO | F1 | l DS | MIPI RX data lane O negative input |
MRXDP1 | E1 | I DS | MIPI RX data lane 1 positive input |
MRXDN1 | D1 | I DS | MIPI RX data lane 1 negative input |
MRXDP2 | H2 | 1DS | MIPI RX data lane 2 positive input |
MRXDN2 | H1 | I DS | MIPI RX data lane 2 negative input |
MRXDP3 | E2 | I DS | MIPI RX data lane 3 positive input |
MRXDN3 | D2 | I DS | MIPI RX data lane 3 negative input |
CCLK | J3 | O | Sensor Referenced Clock |
SCK0 | J4 | I/OD | Sensor I2C Clock |
SDA0 | H4 | I/OD | Sensor I2C Data |
SPWDN | H6 | I/O | Sensor power down GPIO |
SRESET | J6 | I/O | Sensor reset GPIO |
GPIO8 | G5 | I/O | GPIO8 |
GPIO9 | G6 | I/O | GPIO9 |
GPIO10 | G4 | I/O | GPIO10 |
PADVDD1 | H5 | P | Sensor PAD VDD |
PVDD33_RX | F3 | P | MIPI RX PAD VDD |
EVDD_RX | E5 F5 | P | MIPI RX Core VDD |
EGND_RX | D4 D5 D6
E3 E4 | G | MIPI RX Core GND |
MTXCP | G8 | O DS | MIPI TX clock lane positive output | Host Power
Domain |
MTXCN | F8 | O DS | MIPI TX clock lane negative output |
MTXDP0 | G9 | O DS | MIPI TX data lane 0 positive output |
|
MTXDNO | F9 | O DS | MIPI TX data lane O negative output |
MTXDP1 | E9 | O DS | MIPI TX data lane 1 positive output |
MTXDN1 | D9 | O DS | MIPI TX data lane 1 negative output |
MTXDP2 | H9 | O DS | MIPI TX data lane 2 positive output |
MTXDN2 | H8 | O DS | MIPI TX data lane 2 negative output |
MTXDP3 | E8 | O DS | MIPI TX data lane 3 positive output |
MTXDN3 | D8 | O DS | MIPI TX data lane 3 negative output |
XMCLK | B2 | l | PLL Master Reference Clock Input |
RESETB | C5 | l | System Reset;(active low with internal
pull-up resistor)
1:Normal mode
0:Reset mode |
SCK2 | C2 | I/OD | Host I2C Clock |
SDA2 | B1 | I/OD | Host I2C Data |
GPIO4 | C4 | I/O | GPIO4 |
GPIO5 | B9 | I/O | GPIO5 |
GPIO6 | H7 | I/O | GPI06 |
GP|07 | J7 | I/O | GPIO7 |
PADVDD2 | D3 D7 | P | Host PAD VDD |
AVDD33_TX | J8 | P | MIPITX PAD VDD |
EVDD_TX | E7 F7 | P | MIPI TX Core VDD |
EGND_TX | E6 F6 | G | MIPI TX Core GND |
CVDD | C3 C6 C7
C8 F4 G7 | P | Chip Global Core VDD | Global Power
Domain |
VSS | A1A2 A3
A4 A5 A6
A7 A8 A9
B3 B4 B5
B6 B7 B8
C1 C9 J1
J2 J5 J9
G3 H3 | G | Chip Global GND |