JSC-LPDDR4X-2GB-JSL4BAG329ZAMF-05A 16Gb LPDDR4x SDRAM

apppapp · 发表于 2023-11-16 10:45

1、LPDDR3、LPDDR4x 之间的比较

		Items	LPDDR3	LPDDR4x
Feature		CLK scheme	Differential (CLK/CLKB)	←
		Data scheme	DDR Single-ended, Bi-Directional	←
		DQS scheme	Differential (DQS/DQSB), Bi-Directional	←
		ADD / CMD scheme	DDR	SDR
		State Diagram	Refer to the datasheet	Refer to the Datasheet
		Command Truth Table	No support BST	Refer to the Datasheet
		Data mask Truth Table	As is	←
		I/O Interface	HSUL_12	LVSTL_06
		Burst Length	8	16, 32(OTF)
		Burst Type	Sequential	←
		No Wrap	No support	←
		# of Bank per channel	8	←
		Organization per channel	x16/x32	x16
		Data Mask	Support (Write)	Support (Masked Write)
		Refresh mode	Auto / Self Refresh	←
		Masked Write	N/A	Support
		DBI	N/A	Support
Addressing		Row	Refer to the Datasheet (CA0 ~ CA9 1clock DDR based)	Refer to the datasheet (2Gb per channel) (CA0 ~ CA5 4clock SDR based)
		Column
		Bank
		Refresh Requirements
AC Parameter		Speed bin [Mbps]	1600/1866	3200/3733/4266
		Read/Write latency	Refer to the Datasheet	Refer to the datasheet
		Core Parameters
		IO Parameters
		CA / CS / Setup / Hold / Deratin
		Data Setup / Hold / Deratin
Special Function		PASR	Support	←
		TCSR	Support	←
		Deep Power Down	No Support	N/A
		Configurable D/S	Support	←
		ZQ Calibration	Support	←
		DQ Calibration	Support1)	Refer to the datasheet
		CA Calibration	Support	←
		Write Leveling	Support	←
Power Supply		VDD1 [V]	1.70 ~ 1.95	←
		VDD2 [V]	1.14 ~ 1.30	1.06 ~ 1.17
		VDDQ [V]	1.14 ~ 1.30	0.57 ~ 0.65
		VDDCA [V]	1.14 ~ 1.30	N/A
IDD Specification Parameters and Test Conditions		IDD Measurement Conditions	As is	BL16 based
IDD Specification Parameters and Test Conditions		IDD Specification	As is	Refer to the datasheet
Pull-down Pull-up Characteristics		w/ ZQ Calibration	As is	←
		w/o ZQ Calibration	As is	←
		w/ VOH Calibration	N/A	Support
		w/o VOH Calibration	N/A	Support
		Temperature and Voltage Sensi- tivity	As is	←
		RZQI-V Curve	As is	←
Input/Output Capacitance1)			Refer to the Datasheet	Refer to the Datasheet
Absolute maximum DC ratings		VDD1 [V]	-0.4 ~ 2.3	-0.4 ~ 2.1
		VDD2 [V]	-0.4 ~ 1.6	-0.4 ~ 1.5
		VDDQ [V]	-0.4 ~ 1.6	-0.4 ~ 1.0
		VDDCA [V]	-0.4 ~ 1.6	N/A
		VIN/VOUT [V]	-0.4 ~ 1.6	-0.4 ~ 1.5
		Tstg [’C]	-55 ~ 125	←
		Input leakage [uA]	As is	-2 ~ 2
Input/Out- put Operat- ing condition	AC/DC Logic Input Levels for Single- ended Signals	CA and CS pins	AC : VREF ± 0.150V / ± 0.135V (1600/1866) DC : VREF ± 0.10V/0.10V (1600/1866)	VREF(CA), Internal VREF
		CKE pin	0.65×VDDCA ~ 0.35×VDDCA	AC : 0.75×VDD2 @ Min VDD2+0.2 @ Max DC : 0.65×VDD2 @ Min VDD2+0.2 @ Max
		DQ pins	AC : VREF ± 0.15V/0.135V (1600/1866) DC : VREF ± 0.10V/0.10V (1600/1866)	VREF(DQ), Internal VREF
		VREF_CA/DQ tolerance	0.49×VDDQ ~ 0.51×VDDQ	Internal VREF
	AC/DC Logic Input Levels for Differen- tial	VIHdiff/VILdiff (AC/DC) tDVAC	As is	TBD
	AC/DC Logic Input Levels for Differen- tial	VSEH/VSEL(AC)	As is	TBD
	Differential Input Cross Point Voltage	VIXCA/VIXDQ	As is	TBD
	Slew Rate defini- tions for Differential	VILdiff /VIHdiff (Max/Min)	As is	TBD
	AC/DC Output lev- els for Differential	VOHdiff / VOLdiff (AC)	As is	TBD
		IOZ	As is	-5 ~ 5
		MMPUPD	As is	TBD
	Single ended out- put Slew	VOH/VOL(AC/DC)	As is	TBD
	Single ended out- put Slew	SRQse	As is	3.5 ~ 9.0
	Differential Output Slew	VOHdiff/VOLdiff(AC)	As is	TBD
	Differential Output Slew	SRQdiff	As is	6.0 ~ 18.0
	Overshoot / Under- shoot	Maximum Amplitude	As is	←
	Overshoot / Under- shoot	Maximum Area	VDD/VSS : 0.1[V-ns]	←
	Driver Output Timing		HSUL_12	LVSTL_06

注：
1) 该参数适用于芯片和封装。

2、主要特点
• 双倍数据速率架构；每个时钟周期两次数据传输
• 双向数据选通（DQS_t、DQS_c），它们与用于在接收器处捕获数据的数据一起发送/接收
• 差分时钟输入（CK_t 和CK_c）
• 差分数据选通（DQS_t 和DQS_c）
• 命令和地址输入CK 正沿；参考 DQS 两侧的数据和数据掩码
• 每个通道有 8 个内部库
• DMI 引脚：正常读写操作时为 DBI（数据总线反转），DBI 关闭时用于屏蔽写入的数据屏蔽 (DM)
- 当 DBI 打开时，计算屏蔽写入的 DQ 1 的数量
• 突发长度：16、32 (OTF)
• 突发类型：顺序
• 读写延迟：请参阅LPDDR4x AC 时序表
• 每次突发访问的自动预充电选项
• 可配置的驱动强度
• 刷新和自刷新模式
• 部分阵列自刷新和温度补偿自刷新
• 写均衡
• CA 校准
• 内部VREF 和VREF 培训
• 基于 FIFO 的写/读训练
• MPC（多用途命令）
• LVSTLE（低压摆幅终止逻辑扩展）IO
• VDD1/VDD2/VDDQ：1.8V/1.1V/0.6V
• VSSQ 终止
• 无 DLL：CK 到 DQS 不同步
• 边缘对齐数据输出，为数据输入中心对齐编写训练
• 刷新率：3.9us

3、订购信息

Part No.	Org.	Package	Temperature	Max Frequency	Interface
JSL4BAG329ZAMF-05	2Ch, x32	10x15x1.0T(Max), 200-FBGA	Tc = -40 ~ 95°C	3733Mbps	LVSTLE_06
JSL4BAG329ZAMF-05A	2Ch, x32	10x15x1.0T(Max), 200-FBGA	Tc = -40 ~ 95°C	4266Mbps	LVSTLE_06

4、引脚说明及功能图
4.0 引脚说明

Pin Name	Pin Function Channel	Pin Name	Pin Function Common
CK_t, CK_c	System Differential Clock	VDD1	Core Power Supply 1
CKE0	Clock Enable	VDD2	Core Power Supply 2
CS0	Chip Select	VDDQ	I/O Power Supply
CA[5:0]	DDR Command / Address Inputs	VSS	Ground
DMI[1:0]	Input Data Inversion	ZQ0	Reference Pin for Output Driver Strength Calibration
DQS[1:0]_t	Data Strobe Bi-directional	RESET_n	RESET
DQS[1:0]_c	Data Strobe Complementary	DNU	Do Not Use
DQ[15:0]	Data Inputs / Outputs
ODT_CA	On die termination

4.1 功能框图

功能框图

4.2 LPDDR4x 引脚详细说明
[表1] 引脚详细说明

Name	Type	Description
CK_t_A, CK_c_A CK_t_B, CK_c_B	Input	Clock: CK_t and CK_c are differential clock inputs. All address, command, and control input signals are sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c. AC timings for CA parameters are referenced to CK.
CKE_A, CKE_B	Input	Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock circuits, input buffers, and output drivers. Power-saving modes are entered and exited via CKE transitions. CKE is part of the command code.
CS_A CS_B	Input	Chip Select: CS is part of the command code.
CA[5:0]_A CA[5:0]_B	Input	Command/Address Inputs: CA signals provide the Command and Address inputs according to the Command Truth Table.
ODT_CA_A ODT_CA_B	Input	CA ODT Control: The ODT_CA pin is used in conjunction with the Mode Register to turn on/off the On-Die-Termination for CA pins.
DQ[15:0]_A DQ[15:0]_B	I/O	Data Inputs/Outputs: Bi-direction data bus
DQS[1:0]_t_A DQS[1:0]_c_A DQS[1:0]_t_B DQS[1:0]_c_B	I/O	Data Strobe: DQS_t and DQS_c are bi-directional differential output clock signals used to strobe data during a READ or WRITE. The Data Strobe is generated by the DRAM for a READ and is edge-aligned with Data. The Data Strobe is generated by the Memory Controller for a WRITE and must arrive prior to Data. Each byte of data has a Data Strobe signal pair.
DMI[1:0]_A DMI[1:0]_B	I/O	Data Mask Inversion: DMI is a bi-directional signal which is driven HIGH when the data on the data bus is inverted, or driven LOW when the data is in its normal state. Data Inversion can be disabled via a mode register setting. Each byte of data has a DMI signal. This signal is also used along with the DQ signals to provide write data masking information to the DRAM. The DMI pin function - Data Inversion or Data mask - depends on Mode Register setting.
ZQ	Reference	Calibration Reference: Used to calibrate the output drive strength and the termination resistance. There is one ZQ pin per die. The ZQ pin shall be connected to VDDQ through a 240Ω ± 1% resistor.
VDDQ,VDD1, VDD2	Supply	Power Supplies: Isolated on the die for improved noise immunity.
VSS, VSSQ	GND	Ground Reference: Power supply ground reference.
RESET_n	Input	RESET: When Asserted LOW, the RESET_n signal resets all channels of the die. There is one RESET_n pad per die.

4.3 LPDDR4x SDRAM 封装选拔

LPDDR4x SDRAM 封装选拔

注：
1) ODT(CA)_[x] 球连接到 Rank 0 DRAM 芯片的 ODT(CA)_[x] 焊盘。其他等级的 ODT(CA)_[x] 焊盘（如果存在）在封装中被禁用。
2) 如果不使用 ODT 功能，ODT 引脚应视为 NC。
3) ODT 将连接到等级 0。等级 1 的 ODT 输入（如果存在第二等级）将连接到封装中的接地

4.4 LPDDR4x SDRAM 封装尺寸

LPDDR4x SDRAM 封装尺寸

JSC-LPDDR4X-2GB-JSL4BAG329ZAMF-05A 16Gb LPDDR4x SDRAM

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JSC-LPDDR4X-2GB-JSL4BAG329ZAMF-05A 16Gb LPDDR4x SDRAM