特征
[uMCP]
● 工作温度
- (-25)℃ ~ 85℃
● 封装
- 254球FBGA
- 11.5x13.0mm2, 1.2t, 0.5mm 间距
- 无铅和卤素
[ UFS ]
• 兼容UFS2.1
- 向后兼容UFS2.0
• 工作电压范围
- Vcc（与非）：2.7V - 3.6V
- Vccq (CTRL)：未使用
- Vccq2（CTRL）：1.7V - 1.95V
• 温度
- 工作温度（-25℃ ~ +85℃）
- 储存温度（-40℃ ~ +85℃）
• 参考
- JEDEC UFS 规范 V2.1
- MIPI UniPro 规范 V1.61
- MIPI M-PHY 规范 V3.0
• 支持的功能
- 擦除/丢弃/清除/擦除
- 脉宽调制G1~G4 / HS-G1~G3
- 1升/2升
- 命令队列/缓存
- RPMB / 启动LU
- 开机/硬件/端点/LU 重置
- BKOP
- 高优先级逻辑单元
- 可靠的写入操作
- 写保护，安全写保护
- 任务管理操作
- 安全移除型
- 电源管理操作
- 支持 MAX 32 LU
- 设备健康描述符
- 现场固件升级
[ LPDDR4X ]
· VDD1 = 1.8V（1.7V 至 1.95V）
· VDD2 = 1.1V（1.06V 至 1.17V）
· VDDQ = 0.6V（0.57V 至 0.65V）
· 具有 VSSQ 终止功能的可编程 CA ODT 和 DQ ODT
· VOH补偿输出驱动器
· 单数据速率命令和地址输入
· 数据总线双数据速率架构；
- 每个时钟周期两次数据访问
· 差分时钟输入（CK_t、CK_c）
· 双向差分数据选通（DQS_t、DQS_c）
· DMI 引脚支持写数据屏蔽和 DBIdc 功能
· 可编程 RL（读取延迟）和 WL（写入延迟）
· 突发长度：16（默认）、32 和即时
- 飞行模式由 MRS 启用
· 支持自动刷新和自刷新
· 支持所有银行自动刷新和定向每银行自动刷新
· 自动 TCSR（温度补偿自刷新）
· PASR（部分阵列自刷新）通过 Bank Mask 和 Segment Mask
· 后台ZQ校准
功能框图
UFS
UFS功能框图
DRAM
DRAM
订购信息
| Part Number | Memory Combination | Operation Voltage | Density | Speed | Package | | H9HQ21AFAMZDAR-KEM | UFS
LPDDR4X | 3.3V
1.8V/1.1V/0.6V | 256GB (x8)
8GB (x16) | 400Mhz
DDR4 4266 | 254Ball FBGA
(Lead & Halogen Free) |
订购信息
球分配
注意： 1. 供应商特定功能 (VSF) - 该端子不应有任何外部电气连接，但可以有内部连接。 终端可以被路由以提供可访问性并且可以用于通用供应商特定操作。
UFS引脚说明
| Name | Type | Pin No. | Description | | Vcc | Supply | B8~9, C8~9, E8, K8, N8~9, P8~9 | 3.3V supply voltage for the memory devices | | Vccq | Supply | A4~5, B4~5, C4~5, E5, F5 | 1.2V supply voltage for the memory controller Not used internally for SK hynix’s UFS2.1 | | Vccq2 | Supply | A6~7, B6~7, C6~7, K6~7 | 1.8V supply voltage for the memory controller | | VDDi | Input | A9 | Input terminal to provide bypass capacitor for internal regulator.
No need to connect external capacitor. Not used internally | | VDDiQ | Input | A3 | Input terminal to provide bypass capacitor for internal regulator.
Connect 1µF capacitor from VDDiQ to ground. | | VDDiQ2 | Input | A8 | Input terminal to provide bypass capacitor for internal regulator. Connect 1µF capacitor from VDDiQ2 to ground. | | Vss | Supply | B2, B11~12, C1~3, C11~12, D3, D12~14, E1~3, E12, F3, F12~14, G1~3, G10, G12, H3, H5, H10, H12~14, J1~3, J5, J12, K3, K5, K12~14, L1~3, L12, M3~5, M12~14, N2~5, N11~12, P4~5, P11~12 | Supply voltage ground | | RST_n | Input | H2 | Input hardware reset signal. This is an active low signal. | | REF_CLK | Input | H1 | Input reference clock | | DIN0_t DIN0_c | Input | F1 / F2 | Downstream data lane 1. Differential input signals into UFS device from the host. DIN0_t is the positive node of the differential signal pair. | | DIN1_t/ DIN1_c | Input | D1 / D2 | Downstream data lane 2.
Differential input signals into UFS device from the host. | DOUT0_t
/ DOUT0_c | Output | K2 / K1 | Upstream data lane 1.
Differential output signals from the UFS device to the host. DOUT0_t is the positive node of the differential signal pair. | DOUT1_t
/ DOUT1_c | Output | M2 / M1 | Upstream data lane 2.
Differential output signals from the UFS device to the host. | | C+/C- | Input | A12 / A11 | Optional charge pump capacitor terminal. Not used internally for SK hynix’s UFS2.1 | | CPOUT1/ CPOUT2 | Input | A10 / B10 | Optional charge pump output capacitor terminal. Not used internally for SK hynix’s UFS2.1 | | NC | Input |
| No connect | | RFU | - |
| Reserved for Future Use | | VSF | - | E6, E7, E9, E10, F10, G5, J10, K10, P10 | Vendor Specific Function. SK hynix uses G5, E10, K10, P10 as VSF pin |
DRAM 引脚说明
| Symbol | Type | Description | CK_t_A, CK_c_A
CK_t_B, CK_c_B | Input | Clock: CK_t and CK_c are differential clock inputs. All address, command,
and control input signals are sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c. AC timings for CA parameters are refer‐ enced to CK. Each channel (A & B) has its own clock pair. | CKE_A
CKE_B | Input | Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal
clock circuits, input buffers, and output drivers. Power-saving modes are entered and exited via CKE transitions.
CKE is part of the command code. Each channel (A & B) has its own CKE sig‐
nal. | CS_A
CS_B | Input | Chip Select: CS is part of the command code. Each channel (A & B)
has its own CS signal. | CA[5:0]_A,
CA[5:0]_B | Input | Command/Address Inputs: Provide the Command and Address in-
puts according to the Command Truth Table. Each channel (A&B) has its own CA signals. | ODT_CA_A
ODT_CA_B | Input | CA ODT Control: The ODT_CA pin is used in conjunction with the
Mode Register to turn on/off the On-Die-Termination for CA pins. | DQ[15:0]_A,
DQ[15:0]_B | I/O | Data Input/Output : Bi-direction data bus. | DQS[1:0]_t_A,
DQS[1:0]_c_A,
DQS[1:0]_t_B, DQS[1:0]_c_B | I/O | Read Strobe: DQS_t and DQS_c are bi-directional differential output
clock signals used to strobe data during a READ or WRITE. The Data Strobe is generated by the DRAM for a READ and is edge-aligned with Data. The Data Strobe is generated by the Memory Controller for a WRITE and is center aligned with Data. Each byte of data has a Data Strobe signal pair.
Each channel (A & B) has its own DQS strobes. | DMI[1:0]_A,
DMI[1:0]_B | I/O | Data Mask Inversion: DMI is a bi-directional signal which is driven
HIGH when the data on the data bus is inverted, or driven LOW when the data is in its normal state. Data Inversion can be disabled via a mode register setting. Each byte of data has a DMI signal. Each chan- nel (A & B) has its own DMI signals. | | ZQ | Reference | Calibration Reference: Used to calibrate the output drive strength
and the termination resistance. There is one ZQ pin per die. The ZQ pin shall be connected to VDDQ through a 240-Ω ± 1% resistor. | | VDD1, VDD2, VDDQ | Supply | Power Supplies: Isolated on the die for improved noise immunity. | | VSS | GND | Ground Reference: Power supply ground reference. | | RESET_n | Input | RESET: When Asserted LOW, the RESET pin resets both channels of
the die. |
封装信息
254 球 0.5mm 间距 11.5mm x 13.0mm FBGA [t = 1.2mm（最大值）]
SKhynix H9HQ21AFAMZDAR 256GB UFS (x8) / LPDDR4X 64Gb(x16, 2CH/2CS)uMCP规格书下载
|
已绑定手机
发表于 2023-11-17 14:49
